The object of the invention is a method according to the preamble of claim 1 for attenuating transients caused by the transmission system""s justification events in a desynchroniser. The invention also relates to a circuit arrangement for realising the method.
In order to standardise and improve digital communication by wire the synchronous digital hierarchy was developed in order to replace the present, the so called plesiochronic system. As a concept the synchronous digital hierarchy means firstly that all nodes in a digital communications network are basically synchronised to the same clock, and secondly that the transmitted data is arranged into frames, which are defined on several levels according to a hierarchic order. The essential definitions regarding the operation of the arrangement are contained in the ITU specifications G.703, G.70X (Draft) and G.781-G.784. The transmitted data frames are called STM-N frames, where STM is an abbreviation for Synchronous Transport Module and N refers to the number of the hierarchy level. The frames of the lowest hierarchy level are STM-1 frames and they are used for instance in the present 2, 8, 34 and 140 Mbit/s PCM systems. for packing the transmitted data. The transmission rate of the STM-1 frames or the so called basic rate in the SDH system is 155,520 Mbit/s. On the higher hierarchy levels the transmission rates are multiples of this lowest level rate.
The structure of an STM-1 frame is illustrated in FIG. 13. It can be represented by a matrix having 9 rows and 270xc3x97N columns. The matrix elements are bytes, so that one frame contains 2430xc3x97N bytes. The 9xc3x97N first columns of the matrix comprise header and address information, so that the rows 1 to 3 and 5 to 9 of these columns belong to the so called section overhead (SOH) and the row 4 comprises the pointers of so called administrative units (AU). The rest of the STM-1 transmission frame comprises one or more administrative units. The example shows an AU unit AU-4 of the highest level, in which, correspondingly, is placed a highest level virtual container VC-4 in which for instance a 139264 kbit/s plesiochronic information signal can be directly mapped. Alternatively the transmission frame STM-1 can contain several lower level AU units, and into each of these unit is placed a virtual container VC of the corresponding lower level. In FIG. 13 the VC-4 on the other hand is formed by a path overhead POH of one byte and an information bit group of 240 bytes, whereby a particular control byte is placed at the beginning of each. Some of these control bytes are used i.a. to perform the interface justification in connection with the mapping, when the rate of the mapped information signal is slightly offset from its nominal value. The mapping of the information signal into the transmission frame STM-1 is described for instance in the patent applications AU-B-34689/89 and FI-914746.
A tributary unit (TU) forms the connection between a higher and a lower hierarchy level. It comprises a payload, or the VC frame, and a pointer, which indicates where the payload is positioned in the TU frame. The administrative unit (AU) and the tributary unit (TU) differ in that the AU is an assembly which can be cross connected in the network and transmitted between different STM signals, but the TU is an internal unit of a particular frame, and the TU can not be transmitted between different STM-1 signals without an administrative unit of a higher level. One or more tributary units (TU) having a fixed position in a higher level VC frame form a tributary unit group (TUG), which is formed by multiplexing the TU""s. A group can be formed by tributary units of different sizes.
A container (C) is the synchronous payload of each VC. It comprises a payload signal whose frequency can be justified when required so that will be synchronous with the corresponding STM-1 signal. In the future a container can also be a broadband signal.
Each byte in the AU-4 unit has a position number. The above mentioned AU pointer contains the address of the position of the first byte of the VC-4 container in the AU4 unit. With the aid of the pointers it is also possible to perform so called positive or negative pointer justification in different points of the SDH network. If a network node operating at a certain clock frequency receives from the outside a VC having a clock frequency which is higher than the above mentioned the result will be that the data buffer is filled. Then a so called negative justification must be performed. Then one byte from the received VC container is moved to the header side and the number of the pointer is correspondingly reduced by one.
On the other hand, if a received VC has a lower rate than the clock rate of the node, then the data buffer tends to empty, and a positive justification must be made, where a fill byte is added to the VC container, and the pointer value is increased by one.
Both the bit justification used in mapping (interface justification) and the above mentioned pointer justification generate phase jitter, which the desynchroniser should be able to equalise at the exit from the SDH network. Phase jitter and its equalisation is described for instance in the lecture xe2x80x9cSimulation results and field trial experience of justification jitterxe2x80x9d by Ralph Urbansky, 6th World Telecommunication Forum, Geneva, Oct. 10-15, 1991, International Telecommunication Union, Part 2, Vol III, p. 45-49.
Two principles for filtering jitter and fluctuations have been adopted in SDH desynchronisers. The simpler of these is based on a phase-locked loop (PLL) and it is often called a xe2x80x9cnarrow bandwidth desynchroniserxe2x80x9d, because the filtering of even the worst pointer justification events (PJE) is made only with this phase-locked loop. The more complex solution is called a xe2x80x9cbit-leaking desynchroniserxe2x80x9d, because PJE phase hits are prejustified in a jitter spreading process (=bit spreading) before the actual PLL loop. In a bit-leaking desynchroniser the bandwidth of the PLL loop is about one decade wider than the bandwidth of the PLL loop in a narrow bandwidth desynchroniser.
For this purpose the known desynchronisers comprise a data buffer, to which is connected an analogue phase-locked loop, with which the data buffer read clock is phase-locked to the read clock. As the phase-locked loop acts as a low-pass filter it removes the jitter, except components at the lowest frequencies. For instance the SDH pointer justification generates typically much stronger jitter components than the bit stuffing, because single phase hits in the pointer justification are for instance 8 or 24 frame unit intervals UI, and because the frequency of the phase hits caused by pointer justification can represent a very low frequency, which is poorly filtered in the phase-locked loop of the desynchroniser. A sufficient attenuation of the pointer jitter with the aid filtering would require that the bandwidth of the loop is designed to be very narrow (the absolute value depends on the rate of the interface in question). The FIGS. 14 and 15 show how the jitter peaks of two pointer phase hits of 24 UI (measured at the desynchroniser output by a measuring filter defined by ITU) can be reduced with strong filtering to an acceptable peak level of about 0.2 UI, when the bandwidth of the phase-locked loop at the rate 140 Mbit/s is about 2 Hz. However, no pointer justifications are required in normal operating conditions, and only the interface bit justifications are active. Thus the dimensioning of the phase-locked loops of the desynchronisers on the basis of pointer phase hits is un-reasonable, because regarding the bit stuffing the bandwidth of the phase-locked loop could be even ten-fold. Then the locking of the loop would also be more reliable and the locking time would be substantially shorter.
A known solution to this problem is the so called bit leaking, where the phase hits caused by the pointer are removed in a non-linear process (in the time domain), which treats the input data bits in a separate serial buffer so that the phase of the write clock and the data supplied to the actual desynchroniser is cyclically shifted forwards (or backwards), and in this way the step-like phase hit is transformed into a linear phase shift performed during a longer interval. Then the pointer phase hits are treated separately with a bit leaking buffer, whereby the phase-locked loop of the actual desynchroniser can be dimensioned with a wider bandwidth according to the requirements of the bit stuffing. Problems with the xe2x80x9cbit leakingxe2x80x9d solution are the serial data processing on the bit level and the rather complicated logic. In principle the bit leaking solution is better, but in practice the intelligence of the bit leaking circuits seems insufficient for the filtering of special PJE sequences, because they can not detect all special forms of the PJE sequences. Further the effects of the noise in the network clock and the deficiencies of the internal circuit design can be disadvantageous, because they are not filtered as effectively as in the narrow bandwidth solution. Further it must be noted that it is not sufficient to process one pointer at a time, but in the worst case the logic should be able to process tens of interleaved pointer phase hits in different cancellation phases. Thus the use of said technique in a fast 140 Mbit/s desynchroniser is not considered practical i.a. due to the increased power consumption.
The narrow bandwidth design is in principle simple and uncomplicated, but the locking of it requires extra circuits, and it is not completely transparent to a tributary unit signal. Frequency offset transients in the tributary signal, such as the alarm indication signal (AIS) switching and the channel switching, tend to generate heavy and long variations in the filling of the data buffer, or data delays. The delay is not determined by the 0.3 Hz bandwidth, but the long delay depends on the shorter time constant of the second order PLL loop amplifier, which is reflected into the final result as time constants of 10 s, 20 s, . . . or more.
In practice there are further incompatibility problems: the desynchroniser must be sufficiently robust, so that it can co-operate with mappers, pointer processors and clock sources of other manufacturers, and so that it can function disregarding design errors or abnormal behaviour of other manufacturer""s equipment. Thus good test results in the own testing environment or in an environment with self-manufactured equipment do not always guarantee proper operation in the field.
The object of the invention is to provide a simple and advantageous arrangement for by-passing tributary signal clock frequency hits in a desynchroniser which is also suited for 140 Mbit/s and higher rates. A primary object is an additional circuit arrangement in a narrow bandwidth desynchroniser. A particular object is to avoid problems, which are caused when the desynchroniser buffer is filled, or problems caused by a strong oscillation which occur in common solutions with one phase-locked loop.
The title of the Finnish patent no. 95636 is xe2x80x9cDesynkronisaattori ja menetelmxc3xa4 osoitinvxc3xa4rinxc3xa4n vaimentamiseksi desynkronisaattorissaxe2x80x9d (A desynchroniser and a method to attenuate pointer jitter in a desynchroniser). In this method the phase jitter caused by the phase hits in the desynchroniser""s input signal are modulated to a frequency, which is substantially higher than the bandwidth of the phase-locked loop.
The title of the Finnish patent no. 90709 is xe2x80x9cJxc3xa4rjestely osoitinvxc3xa4rinxc3xa4in vaimentamiseksi desynkronisaattorissaxe2x80x9d (An arrangement for attenuating pointer jitter in a desynchroniser). In this arrangement the jitter amplitude caused by justification operations is attenuated by means, with which the phase-locked loop is forced, synchronised to the occurrence of each justification, to limit the maximum amplitude of the phase jitter caused by said pointer justification in the desynhcroniser output signal.
However, in these patents no transparency is provided in the desynchroniser to transients appearing in the tributary unit clock signal.
The objects of the present invention mentioned above are attained with a method according to the invention, which is presented in the characterising clause of claim 1.
As noted above, the frequency of occurrence of phase hits caused by the pointer justifications may represent a very low frequency, which is not readily filtered in the phase-locked loop of the desynchroniser. The inventive idea is to by-pass the phase-locked signal so that the transient acts directly on the oscillator of the phase-locked loop, whereby the oscillator substantially conveys the transient to the address counters of the desynchroniser. Then, particularly in a narrow bandwidth desynchroniser, a substantially lower output jitter is obtained. Here it must be noted that a phase transient of the tributary unit signal is not jitter, but a signal characteristic.
A circuit arrangement realising the method according to the invention is presented in claim 5.
The signal processing according to the invention can be performed digitally, in a byte based 8-bit parallel mode which is natural to SDH, and which is used also in other connections in the desynchroniser.
The by-pass method according to the invention avoids problems caused by buffer filling or wide oscillations, which occur in conventional solutions with a single phase-locked loop. The method can be applied in any desynchroniser at any bit rate, but a particularly good result is obtained in a narrow bandwidth desynchroniser, as is shown below.
In principle the by-pass method of the present invention can be regarded as a feed forward control of the tributary signal""s phase. The signal supplied to the by-pass input is obtained by studying the AU/TU-pointers in a way known per se. Then the phase-locked loop PLL and its feedback system only has to make the fine adjustment of a phase hit caused by the transient in the tributary signal.
In principle the method according to the invention could be applied also in other systems, and not only in the case of SDH.
The patent publication EP 0 481 847 A1 presents a device for attenuating jitter caused by pointer justification in a digital telecommunications network. The device contains a circuit with which justification bits are added adjacent to the phase hit caused by the pointer justification, whereby the justification bits are intended to remove the effects of these phase hits after they have passed through a conventional desynhcroniser. A control circuit is also arranged in the device so that when the phase hits caused by pointer justification comprise several bits, the control circuit divides the hits into hit elements and controls the addition of such elements in a manner which is adjusted according to the occurrence frequency of the pointer justifications. This concerns the justification of phase hits of the PJE type by performing a compensation. The compensation is in other words made by adding artificial partial phase hits adjacent to the PJE phase hit so that the abruptness of the whole hit is filtered. In contrast to this, the present invention proposes a solution where the clock PJE phase hits, the reference clock hits, etc., are filtered with a slow PLL circuit, as is common in the industry. Moreover, such phase hits which represent the clock contents (bit stuffing) of the tributary signal are corrected in a by-pass of the phase-locked loop. Without the by-pass solution a desynchroniser using the slow PLL would not be transparent for all such phenomenons which are allowed to the tributary unit signal.
With the aid of the arrangement according to the invention the transparency of the desynchronisers of the mentioned type will be substantially improved.
The bit stuffing by-pass method according to the invention can be applied in all desynchronisers. In a narrow bandwidth desynchroniser the method according to the invention presents two important advantages:
1) The amplitude of buffer filling variations is only one tenth or smaller than in the original narrow bandwidth desynchroniser. This means that the desynchroniser is transparent at the tributary signal interface for all specifications.
2) In the original desynchroniser the tail of the buffer fill is of the order of tens of seconds, but with the by-pass method according to the invention it will kept shorter than 0.5 s. Therefore in a desynchroniser according to the invention there occurs no interfering tributary signal delays after a transient. The ITU recommendations define 1 second as the longest switch-over time, and due to the shorter tail effect the arrangement according to the invention can better fulfil this recommendation. This is advantageous in an ITU reference model examination, where the emphasis is put on the function of the frame buffers of the switching arrangement, because no delay shares are defined for the desynchroniser.
According to the invention the best function is obtained so that the response of the VCO oscillator to the signal on the by-pass path exactly corresponds to a change in the frequency offset of the original tributary signal. This is obtained by using components with tight tolerances. However, the arrangement according to the invention provides advantages also when the tolerances do not enable a complete by-pass response at the output of the VCO.